NAND-based flash memory systems include a translation layer (“FTL”) that maps host logical block addresses (“LBAs”) into physical addresses in NAND flash memory. In high-performance products such as solid state drives (“SSDs”), a table that maps LBAs to physical addresses is stored in local dynamic random-access memory (“DRAM”) in order to reduce latency. Typically, a ratio of DRAM consumed for mapping tables to a total capacity of the memory system is 1:1000-1 MB of table data is required to effectively address 1 GB of NAND flash memory. The performance difference is considerable—while NAND flash memory access is typically a minimum of 50-70 μs per read, local DRAM is typically accessed on the order of hundreds of ns per read.
In an effort to reduce costs in high-performance non-volatile memory systems, it has become desirable to reduce or eliminate DRAM usage. As a result, non-volatile memory systems include a feature called a host memory buffer (“HMB”). The host memory buffer allows the usage of a designated space in memory of a host system such as a RAM cache for transition layer tables (FTL tables).